Electronics For You

Accelerating RISC-V Verification With Quality And Security At The Core

As the RISC-V ecosystem grows, startups struggle to verify complex chips before tape-out. Chennai-based startup addresses ...
EDN

Leveraging system models for RTL functional verification

Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet ...
EDN

TLM-Driven Design and Verification using Cadence®

Transaction level modeling (TLM) is gaining favor over register-transfer level (RTL) for design components because of its many advantages—including faster design and verification times, easier ...
Semiconductor Engineering

TLM-Driven Design And Verification—Time For A Methodology Shift

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced ...
Electronic Design

Speeding to a Verification Solution

According to Intel, the number of silicon bugs that need to be eliminated before tapeout is increasing over 200% per generation, a rate even faster than a Moore's Law increase. Evidently, each ...
Electronic Design

TLM-Based Verification Finds Strength In Standards

In design automation, as in other areas of the electronics industry, technologies and methodologies find broad acceptance through standardization. For example, the standardization of the Verilog ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...